Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are synthesis, placement, and routing of the system on the target device.
After a system has been synthesized, placed, and routed on a target device, it is important that the system achieves timing closure where all timing constraints in the system are met in order to ensure proper functionality. Long-path timing constraints, where delays of given paths are less than a maximum value, is an example of a timing constraint that is occasionally violated resulting in timing failure of a design.
In the past, some prior art tools attempted to help designers achieve timing closure by utilizing a static set of heuristics that applied generally to the EDA tool. The guidance provided by these prior art tools relied on global CAD settings to solve timing closure problems and did not address issues related to a specific system. Other prior art tools attempted to help designers with timing closure by providing raw information about timing failures. With these tools, the designer was left with the task of interpreting the data and drawing his own conclusions on how to use the data to resolve timing issues.